In what is considered one of the most groundbreaking announcements ever made to the international tech industry, IBM has revealed what it calls the world’s first chip technology, which breaks the 1-nanometer barrier. This technology has been demonstrated on the 0.7 nm node—which is the same as 7 angstroms—bringing semiconductors into the era of atomic-level design. The announcement, made at IBM’s research facility in Yorktown Heights, New York, is considered one of the most important innovations in chip design in recent decades, according to experts who believe it can prolong Moore’s Law for at least a decade.
For over half a century now, the semiconductor industry has been working on the basis of what has been known as Moore's Law—the notion stating that the number of transistors on a computer chip would double every other year and thus make them faster and better.
However, for most of the time, engineers were achieving that by shrinking the size of transistors—the tiny electronic switches used to perform calculations. But that method has been failing them lately. Transistors have become so small within the last 15 years that the peculiarities of quantum physics start affecting their work.
IBM's solution to the problem is the nanostack—a completely new concept of building transistors.
This innovative design of IBM’s new chip lies in its novel three-dimensional transistor architecture. While in traditional computer chips, transistors sit flat on a silicon surface, in the nanostack architecture, the transistors are vertically stacked and staggered in two planes with the technique known as "3D sequential integration."
This seemingly simple change unlocks several powerful advantages:
1. Increase in transistor density: In contrast to the previous designs that spread transistors outwards, the latest chip features nearly 100 billion transistors that occupy an area about the size of a fingernail—almost double the number in IBM’s 2 nm chip released in 2021.
2. Material versatility: With the help of the staggered design, it becomes possible for engineers to experiment with various combinations of materials in each layer, optimizing the performance and energy consumption of each transistor separately.
3. Easy connection: Since the transistors of the second layer do not stack on top of those of the first layer but are staggered, connecting these layers becomes much easier.
The nanostack builds on an existing approach called "nanosheet technology"—itself invented by IBM and now used across the industry as the current leading-edge architecture. However, where nanosheet technology operates in a single flat plane, the nanostack takes the concept into a new vertical dimension.
The numbers IBM is claiming for the nanostack chip are striking. Compared to its own 2 nm chip—already among the most advanced in the world—the new technology is projected to deliver:
- Up to 50% higher performance
- Up to 70% higher energy efficiency
- 40% increase in SRAM scaling, which is high-speed memory near processors
The latter is especially noteworthy from an artificial intelligence perspective. The SRAM bandwidth is becoming one of the most important issues that prevent AI chips from operating more efficiently. By making the memory smaller and faster, it would be possible to send data to the processor faster, thus providing more computational capacity and less consumption of electricity in AI facilities all over the world.
IBM did not just draw up the nanostack on paper. The company proved the validity of the design through a number of experiments, including:
1. Atomically thin dielectric bonding in CMOS integration, proving that the layers can be bonded at the atomic level
2. Dual-channel engineering capability, proving that the transistors in each layer can be independently engineered
3. Functioning CMOS inverter, proving that the chip can perform computations of digital logic with expected switching characteristics
The following tests, conducted at the well-regarded VLSI 2026 conference, verify that the nanostack design is not just theoretical; it is possible to fabricate the nanostacks, and computation is possible with them.
IBM has designed a sub-1-nm chip along with its research ecosystem at the IBM semiconductor plant in Albany, New York. There will also be an installation of the High NA EUV lithography equipment at the same location. This is a product from Dutch firm ASML. IBM will collaborate on the development of High NA EUV processes with firms like Lam Research Corp., Tokyo Electron (TEL), and SCREEN Semiconductor Solutions.
First of all, it is worth mentioning that 3D stacking of transistors is not the exclusive route that IBM decided to go down. There are leading companies in the sphere of computer chip making, like Intel, Samsung, TSMC, and even the Belgian research center Imec, which are already engaged in CFETs (complementary field-effect transistors) creation.
However, there is one unique feature concerning IBM's design of nanostacking. As opposed to the designs in which transistors of the second layer are located exactly above the transistors of the first layer before the bonding process, in IBM's design, staggered nanosheets are used for better aligning of the two layers.
Moreover, this is extremely important for atomically tiny elements because any misaligning can considerably decrease their effectiveness.
In addition, IBM's approach differs from one of another popular design, namely AMD's 3D V-cache technology.
The markets reacted very quickly to the announcement. Shares of IBM went up by over 6% in pre-market trade on the day of the announcement. The high degree of optimism stems from the wider acknowledgment that IBM is making a significant move towards securing a place in the future of semiconductor research while its competitors Nvidia and Intel dominate today’s commercial chip industry.
The importance of the move was expressed by Jay Gambetta, IBM Fellow and Director of IBM Research: "It is not a minor step forward; it is a major leap forward." Gambetta believes that within a decade chips produced using nanostacking technology will be extensively used in data centers, where the enhanced efficiency will help meet the power requirements of contemporary AI infrastructure.
Furthermore, IBM has recently announced its intention to create a separate company called Anderon, which would be considered to be the first-ever pure-play quantum foundry. The new independent entity of IBM will utilize its semiconductor expertise and the quantum computing experience to ensure the leadership of the United States in quantum wafer production.
As big as the announcement may be in terms of research achievements, it should not be overlooked that at present the nanostack processor is merely a prototype, tested in laboratory conditions. The company’s goal is to take the technology to market within five years, so we can expect its launch sometime during the early 2030s.
Although the term "0.7 nm" is, according to tradition in the industry, used to define a generation of manufacturing processes rather than the actual size of all features of each transistor, there is no doubt that the engineering involved is truly an advance into angstrom-level scaling.
